1. Field of the Invention
The invention relates generally to a lock detector and, more particularly, to a lock detector used in conjunction with phase-locked loop or similar oscillation circuits.
2. Description of the Related Art
A phase-locked loop (PLL) may require many thousands or millions of cycles before reaching its steady-state locked condition from its initial power-on state. An indication of the locked condition for the PLL is useful as a diagnostic tool or may be used as part of the power-on-reset sequencing for a system during initial power-up. Conventionally, PLL lock detectors are implemented with two or more large frequency counters, and thus may take up valuable space in a circuit area. Moreover, since both the counters are continuously toggling during steady-state locked conditions, the prior-art PLL lock detectors can dissipate significant power. These large frequency counters may also introduce digital switching noise, which can seriously limit the performance of the sensitive analog components of a mixed-signal PLL design. Some of the prior art specifically detects only frequency lock, a condition necessary for phase lock, rather than a more stringent frequency and phase lock. Other prior-art PLL lock detectors use delay lines, which will limit the frequency range for lock detection and are difficult to manufacture with the appropriate tolerances. Also, some other prior-art PLL lock detectors require low-pass filter components, which may take up significant space in a circuit area and require strict manufacturing process controls.
Therefore, there is a need for a lock detector that takes up less space in a circuit area, consumes less power, and detects lock over a wider range of frequency.